This invention relates to decimal multiplication in a superscaler processor. Decimal multiplication is a complex procedure in computer hardware. Generally, the more hardware dedicated to decimal multiplication, the faster the operation can be executed. One hardware intensive method utilizes a linear array of digit multipliers such that each multiplier block is capable of multiplying one decimal digit by one decimal digit. These modules are often implemented with a programmable logic array (PLA), memory device, or combinatorial logic. Although considered fast, with this methodology, significant hardware resources are necessary to implement the solution.
A simple solution requiring a shifter, three registers and a decimal adder builds partial products terms by adding the multiplier to an accumulated sum each cycle. The number of cycles required to compute a partial product is equal to the multiplicand digit being processed. The number of partial products that need to be computed is equal to the number of digits in the multiplicand. Once each partial product is computed the accumulated result is shifted by one digit and the next multiplicand digit is used to compute the next partial product. Although this solution requires little dedicated hardware, it requires a significant number of processing cycles to complete a single multiplication.
There are also methods for reducing the amount of computation required to generate the partial product terms by utilizing additional registers (hardware that might already be available on the processor and was originally intended for other uses). For example, a register file may be used to store all the multiples from 0 to 9 times the multiplier, requiring a 10 register memory array.